Semiconductor Dynamic Random Access Memory (DRAM) devices have many memory cells. Indeed, a memory cell is provided for each bit stored by a DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. The formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits. The capacitor type that has been typically used in DRAM memory cells are planar capacitors, because they are relatively simple to manufacture.
In order to achieve high performance (i.e. high density) DRAM devices, the memory cells must be scaled down in size to the submicrometer range. As the capacity of DRAMs has increased, the size of the memory cells have steadily decreased. If planar capacitors are used, as the memory cells decrease in size, the area of the capacitors also decrease, resulting in a reduction of cell capacitance. For very small memory cells, planar capacitors become very difficult to use reliably. Specifically, as the size of the capacitor decreases, the capacitance of the capacitor also decreases and the amount of the charge capable of being stored by the capacitor similarly decreases. This results in the capacitor being very susceptible to a particle interference. Additionally, as the capacitance decreases, the charge held by storage capacitor must be refreshed often. A simple stacked capacitor can not provide sufficient capacitance, even with high dielectric Ta.sub.2 O.sub.5.
Prior art approaches to overcoming these problems have resulted in the development of the trench capacitor (see for example U.S. Pat. No. 5,374,580) and the stacked capacitor. The trench capacitor has the well known problem of "gated diode leakage," which is the leakage of current resulting in the trench capacitor failing to hold a charge. Reducing the thickness of the dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliability problems.
A new capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG-Si) polysilicon storage node has been developed (see CAPACITOR-OVER-BIT-LINE CELL WITH HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs", M. Sakao et al., microelectronics research laboratories, NEC Corporation). The HSG-Si is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous-Si to polycrystalline-Si. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufactured by optical delineation. The HSG-Si storage node can be fabricated by addition of two process steps, i.e. HSG-Si deposition and a etchback. A HSG-Si electrode node has been proposed (see
NEW CYLINDRICAL CAPACITOR USING HEMISPHERICAL-GRAIN Si FOR 256 Mb DRAMs", H. Watanabe et al., microelectronics research laboratories, NEC Corporation). After the electrode structure is formed, a native-oxide on the electrode surface is removed by a diluted HF solution. HSG-Si appeared on silicon surface using eeding method".